Ceramic Bga Reliability
In addition the utilized ceramic ball grid array cbga.
Ceramic bga reliability. Plastic bga pbga ceramic bga cbga pwb 63sn 37pb eutectic flip chip flip chip bga fcbga column cbga ccga 90pb 10sn high melt i o 600 i o 600. The cookies we use can be categorized as follows. Ball grid array bga assembly reliability jpl nepp presentation ipc 9701 csp thermal cycle created date. Also utilized was a 256 leaded and a 256 plastic bga package for evaluating and directly comparing manufacturing robustness and reliability.
Assemblies with water soluble flux were cleaned in an electrovert h500. Lower cte may be used to increase reliability. Shih et al reliability of hitce ceramic bga packages to be published 2005. Incoming pcb requirements for cbga freescale semiconductor.
Substrate based ball grid array bga flip chip bga quad flat leadless stacked chip scale flip chip csp xuejun fan moisture related reliability xuejun fan lamar edu higher performance smaller size cheaper price chip scale and wafer level packaging csp wlp. Large number of vias within area of bga increases cte locally. Ceramic ball grid array packaging assembly reliability freescale semiconductor. Ceramic plates and printed circuit boards pcb to assess solder wetting.
A small tape based plastic bga package with 280 balls was included in the study 16 x 16 mm 0 8 mm pitch 9 x 9 depopulated center. Madsen abstract the white paper component reliability after long term storage texas instruments application. Bga package component reliability after long term storage r. Flip chip hitce ltcc bga package kyocera provides both ceramic and organic packages for large scale integration lsi devices.
Balls for this package are 90 pb and 10 sn and attached to the ceramic substrate using eutectic 63sn 37pb solder paste. Type 1 ceramic and plastic bga packages with nearly 300 i os. Type 2 ceramic and plastic bga packages with nearly 600 i os. Typically these are packaged in organic or ceramic ball grid array bga packages which cover a wide range of package input output i o capabilities required for high performance devices.